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-- Company: 
-- Engineer:
--
-- Create Date:   23:42:23 10/05/2009
-- Design Name:   
-- Module Name:   /usa/mcgraw/CPEG422/proj1/program_tx_tb.vhd
-- Project Name:  proj1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: program_tx
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY program_tx_tb IS
END program_tx_tb;
 
ARCHITECTURE behavior OF program_tx_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT program_tx
    PORT(
         data_in : IN  std_logic_vector(127 downto 0);
         clk : IN  std_logic;
         reset : IN  std_logic;
         w_data : OUT  std_logic_vector(7 downto 0);
         tx_full : IN  std_logic;
         wr_uart : OUT  std_logic;
         data_available : IN  std_logic;
         data_ack : OUT  std_logic
        );
    END COMPONENT;


component uart is
   generic(
     -- Default setting:
     -- 19,200 baud, 8 data bis, 1 stop its, 2^2 FIFO
     DBIT: integer:=8;     -- # data bits
      SB_TICK: integer:=16; -- # ticks for stop bits, 16/24/32
                            --   for 1/1.5/2 stop bits
      DVSR: integer:= 163;  -- baud rate divisor
                            -- DVSR = 50M/(16*baud rate)
      DVSR_BIT: integer:=8; -- # bits of DVSR
      FIFO_W: integer:=2    -- # addr bits of FIFO
                            -- # words in FIFO=2^FIFO_W
   );
   port(
      clk, reset: in std_logic;
      rd_uart, wr_uart: in std_logic;
      rx: in std_logic;
      w_data: in std_logic_vector(7 downto 0);
      tx_full, rx_empty: out std_logic;
      r_data: out std_logic_vector(7 downto 0);
      tx: out std_logic
   );
end component;

	
	--Inputs
   signal data_in : std_logic_vector(127 downto 0) := (others => '0');
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal tx_full : std_logic := '0';
   signal data_available : std_logic := '0';
	
   signal rx : std_logic := '0';
   
	
	

 	--Outputs
   signal w_data : std_logic_vector(7 downto 0);
   signal wr_uart : std_logic;
   signal data_ack : std_logic;


   signal rx_empty : std_logic;
   signal r_data : std_logic_vector(7 downto 0);
   signal tx : std_logic;
   

   -- Clock period definitions
   constant clk_period : time := 1us;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: program_tx PORT MAP (
          data_in => data_in,
          clk => clk,
          reset => reset,
          w_data => w_data,
          tx_full => tx_full,
          wr_uart => wr_uart,
          data_available => data_available,
          data_ack => data_ack
        );
   --uart_instance: entity work.uart(arch)
   uart_instance: uart
      generic map(DVSR => 2, DVSR_BIT => 2)
      port map(clk=>clk, reset=>reset, rd_uart=> '0',
               wr_uart=>wr_uart, rx=>rx, w_data=>w_data,
               tx_full=>tx_full, rx_empty=>rx_empty,
               r_data=>r_data, tx=>tx);
   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.
		reset <='1';
      wait for 10us;	
		reset <='0';
	
		data_in <= x"617765736f6d65207368697400000000";
		data_available <= '1';
		
      wait for clk_period;
		data_available <= '0';

      wait for clk_period*100;
		

      -- insert stimulus here 

      wait;
   end process;

END;
